Computing devices, including for example multi-core processors, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), may often incorporate several processes or subsystems that each require access to random access memory (RAM).
These processes or subsystems may be part of a system (e.g. a system-on-a-chip (SoC)) that provides a particular set of functions, or may each provide a different function. For example the device may be an ASIC that includes a different subsystem for each of three modems for a wireless device, such as a GSM (Global System for Mobile Communications) modem, a 3G (3rd Generation radio telecommunication network) modem and an LTE (Long Term Evolution) modem. Each of these subsystems may require RAM access, though in some cases only a subset of the subsystems (e.g. only one modem) may be in use at any particular time. As used herein, “wireless devices” include in general any device capable of connecting wirelessly to a network, and includes in particular mobile devices including mobile or cell phones (including so-called “smart phones”), personal digital assistants, pagers, tablet and laptop computers, content-consumption or generation devices (for music and/or video for example), data cards, USB dongles, etc., as well as fixed or more static devices, such as personal computers, game consoles and other generally static entertainment devices, various other domestic and non-domestic machines and devices, etc. The term “user equipment” is often used to refer to wireless devices in general, and particularly mobile wireless devices.
One approach to providing each subsystem with RAM access is to provide a different RAM device for each subsystem and to provide each subsystem with a memory controller that enables the subsystem to use its corresponding RAM device. This approach has an advantage in terms of the relative simplicity and flexibility of each memory controller and the relatively small number of constraints (e.g. timing and bandwidth constraints) each memory controller enforces on the subsystem that uses it. However providing a separate RAM device for each subsystem is costly and each RAM device will occupy valuable space and/or silicon area. Additionally each memory controller will consume significant silicon area within each subsystem. In cases where only a subset of the subsystems may be in use at a time, this approach can therefore be wasteful.
Another approach to providing each subsystem with RAM access is to share a RAM device between two or more of the subsystems. In this case a memory controller is shared between the subsystems so that they can use the shared RAM device. This approach has an advantage in terms of lower cost, space and silicon area. However, the complexity of the memory controller is increased, for example it may enforce a number of constraints, such as timing and bandwidth constraints on the subsystems that use it. Where more than one of the subsystems needs to access the RAM at the same time, timing issues can become particularly problematic as the otherwise parallel operations of the subsystems must be interleaved with respect to each other in order to allow shared access to the shared RAM. This can mean that this approach requires a memory controller that is difficult to design, and/or that complex additional logic may be needed within each subsystem so that it can handle the shared memory accesses.
In a device where only a subset of the subsystems are typically in use at any one time, it should be noted that there may still be times when two different subsets of subsystems are active, e.g. one subset may be transitioning to an inactive state whilst another subset is transitioning to an active state. For example a device could comprise multiple modems with typically only one modem in use at a time, but several modems may be in use when switching between modems, e.g. a 3G modem transitioning to an inactive state whilst an LTE modem transitions to an active state. In another example, the subsets of subsystems that are in an “inactive” state may still require occasional access to a small amount of RAM, whereas when those subsystems are in an active state, they may require frequent access to a large amount of RAM.
Sharing a RAM between such subsystems is difficult because there are times when several subsystems require access to the RAM, and therefore timing issues may become problematic as discussed above.